As semiconductor device sizes become smaller and smaller, device manufacturing and processing techniques must be carefully monitored in order to determine their effect on the operating parameters of the fabricated semiconductor device. As an example, the parasitic resistance of a semiconductor device can vary widely depending upon the particular manufacturing and processing techniques used to fabricate the device. More specifically, in a metal oxide silicon field effect transistor (MOSFET), the total parasitic resistance is comprised of various resistive components. The value of each of the resistive components may vary as fabrication parameters are changed.
With reference now to Prior Art FIG. 1, a side sectional view of a silicided MOSFET is shown. As shown in Prior Art FIG. 1, a conventional silicided MOSFET 100 is comprised of a semiconductor substrate 102 of p-type conductivity. N.sup.+ -type wells 104a and 104b are formed into the p-type substrate. It is understood by those of ordinary skill in the art that silicided MOSFET 100 could also be comprised of p.sup.+ -type wells residing in an n-type substrate. MOSFET 100 further includes lightly doped drain (Ldd) regions 106a and 106b peripherally bordering n.sup.+ -type wells 104aand 104b. Ldd regions 106a and 106b are formed during a doping fabrication step. More specifically, sidewall spacers 108a and 108b, attached to combination gate 110, shield Ldd regions 106a and 106b from heavy doping implantation during the device fabrication process. Thus, regions 106a and 106b are more lightly doped than regions 104a and 104b. A channel region 109 resides between regions 104a and 104b. Combination gate 110, disposed over channel region 109, is comprised of a layer of tungsten silicide 112 disposed over a layer of polysilicon 114. MOSFET 100 also includes silicide regions 116a and 116b which extend across regions 104a and 104b, respectively, and terminate at the edge of Ldd regions 106a and 106b, respectively. Silicided regions 116a and 116b are formed, for example, of titanium silicide, cobalt silicide, and the like. The above-described features are covered by a passivation layer 118 comprised, for example, of silicon dioxide or other dielectric material. Contacts 120a and 120b extend through passivation layer 118 and electrically contact silicided regions 116a and 116b, respectively.
When active, current flows from contact 120a through silicided region 116a, Ldd region 106a, channel region 109, Ldd region 106b, silicided region 116b, and into contact 120b. The above-described current path through MOSFET 100 has various parasitic resistances associated therewith. For example, a contact or interface resistance, R.sub.c, occurs at the interface between each of contacts 120a and 120b and their respective underlying silicided regions 116a and 116b. Each of silicided regions 116a and 116b has a silicide sheet resistance per unit length, .rho..sub.sil, associated therewith. Another contact resistance, R.sub.sil/si, exists at the interface of each of silicided regions 116a and 116b and their respective bordering Ldd region 106a or 106b. Additionally, yet another resistance, R.sub.Ldd, is associated with current flow through each of Ldd regions 106a and 106b.
Referring now to Prior Art FIG. 2A, a Prior Art test structure used to determine the interface resistance, R.sub.c, occurring at the interface between a contact and an underlying silicon region is shown. As shown in Prior Art FIG. 2A, the test structure is comprised of a single test device 200. Single test device 200 is formed of a semiconductor substrate 202 of p-type conductivity. A single n.sup.+ -type well 204 is formed into the p-type substrate. It is understood by those of ordinary skill in the art that single test device 200 could also be comprised of a single p.sup.+ -type well residing in an n-type semiconductor substrate. A passivation layer 206 overlies well 204 and substrate 202. Single test device 200 further includes multiple contacts 208a-208e which extend through passivation layer 206 and electrically contact well 204.
Prior Art FIG. 2B is a top view of single test device 200. As shown in Prior Art FIG. 2B, each of contacts 208a-208e has a length, L, and a width, Z. Additionally, well 204 has a diffusion width, W. In single test device 200, contact 208a is separated from contact 208b by a distance d.sub.1, contact 208b is separated from contact 208c by distance d.sub.2 which is greater than distance d.sub.1, contact 208c is separated from contact 208d by a distance d.sub.3 which is greater than distance d.sub.2, and contact 208d is separated from contact 208e by a distance d.sub.4 which is greater than distance d.sub.3.
Referring next to Prior Art FIG. 3, a graph 300 of the resistance measured between various pairs of contacts 208a-208e of Prior Art FIGS. 2A and 2B is shown. In conventional operation, the total resistance between various pairs of contacts 208a-208d is measured and plotted as a function of the distance separating the measured pair of contacts. In so doing, a line 302 is generated. The y-intercept of line 302, gives twice the value of the contact resistance, R.sub.c, between any of contacts 208a-208e and underlying silicon region 204. Additionally, the sheet resistance per unit length, .rho..sub.si, is given by the slope of line 302.
By plotting the resistances measured using single test device 200, only limited parasitic resistance values are obtained. That is, such a prior art device and method does not determine parasitic resistance components such as the contact resistance, R.sub.c, occurring at the interface between contacts and their respective underlying silicided regions. Such a prior art device and method does not provide the silicide sheet resistance per unit length, .rho..sub.sil. Additionally, single test device 200 and the above-described prior art resistance measuring method does not determine the contact resistance, R.sub.sil/si, caused by the interface of a silicided region and a respective bordering Ldd region. Similarly, prior art single test devices and methods do not determine the resistance, R.sub.Ldd, associated with current flow through an Ldd region.
Thus, the need has arisen for a test structure and method which efficiently determines the total parasitic resistance in a metal oxide silicon field effect transistor (MOSFET). A further need exists for a test structure and method which determines the resistance value of various resistive components comprising the total parasitic resistance.